In the field of analog Phase Locked Loops (PLLs), where the output of the circuit is an oscillator signal, phase locked to an input reference signal, the phase accuracy of the output signal is highly dependent of the input phase detector resolution. The phase detector should preferably also be able to handle large phase errors during acquisition. This is relevant in particular for PLLs with large output frequency range, but moderate phase accuracy requirements where a large sensitivity of the Voltage Controlled Oscillator (VCO) can be used to cover the frequency range. Existing analog phase detectors most commonly have high resolution but cannot detect phase errors larger than 2π radians.
The inability to detect large phase errors results in slow acquisition during, for example, start-up and frequency switching. Even if the phase error is several multiples of 2π, the phase detector will only output a fraction of 2π and indicate that the phase error is smaller than it actually is. The charge pump, which should pull the loop voltage and, in turn, the VCO to the correct frequency, will not work as efficiently as it could. FIG. 8 illustrates a typical behaviour of the control signal to the VCO at a frequency switch. Several methods to circumvent this problem exist, where the most commonly used is switching to a larger bandwidth of the PLL during acquisition.
Examples of such solutions are provided in U.S. Pat. No. 6,281,712 and US 2008/061888. U.S. Pat. No. 6,281,712 discloses a phase detector circuit operating at a high frequency and having a steering circuit operating on frequency-divided versions of the phase detector signals. The phase detector implements steering by adding dividers at both input ports to the steering circuit. US 2008/061888 discloses a multi-loop PLL circuit having a first loop for generating a first control current and a second loop for generating a second control current. Dual frequency dividing functions are provided for feedback clock signals. The frequency of a second reference clock signal is higher than that of a first reference clock signal. The first reference clock signal and one of the feedback clock signals are compared by a first phase/frequency detector of the first loop, and the second reference clock signal and the other of the feedback clock signals are compared by a second phase/frequency detector of the second loop.
U.S. Pat. No. 6,442,225 discloses a multi-phase-locked loop for data recovery which generates and outputs multiple sets of control signals via a multi-phase VCO which generates a plurality of multi-phase clock signals for detecting a transition edge of a data signal. A multi-phase-locked loop without dead zone can thereby be provided.
Another method for faster acquisition is look-up table based pre-charging of the loop filter or capacitance switching in the VCO. Initial measurements of the VCO frequency characteristics are stored in a table and used later on when switching frequency. In that way, frequency acquisition may be almost instantaneous, but requires a phase locking period after switching.
A third method for fast acquisition commonly used for PLLs with large output frequency range and stringent requirements on output phase accuracy, includes digital calibration of the VCO. The loop filter voltage is held constant and the analog loop is replaced by digital circuitry during acquisition. When phase lock is achieved, the analog loop is switched back in again for phase accuracy. The digital loop used during acquisition may have very large bandwidth to speed up settling.
The methods described above improve the settling times to different extents, but also have their downsides. The most commonly used method of switching to a larger bandwidth during settling is normally done by increasing the charge pump current, which yields a larger loop gain. However, this requires some additional measures and circuitry in order not to create instability of the loop, e.g., switching to a smaller loop filter zeroing resistance. However, the available charge pump current still is not very effectively used. An issue with the look-up table approach can be that it requires an initial state at start-up where the VCO characteristics are measured and stored in the look-up table.
The mentioned method of digital calibration during acquisition may be very quick and for PLLs where digital control of the VCO is needed, also to split the VCO tuning curves into several for smaller sensitivity, this is the preferred method. Though it is clear that this requires extensive digital hardware, loop filter pre-charging circuitry and, for PLLs with analog tuning only, digital controllability of the VCO would have to be added.
Still, for pure analog PLLs, there is a need to improve acquisition.